https://siliconandsystems.com/en/ An independent tech review covering semiconductors, computer architecture, systems, and AI infrastructure. Slower than news, easier than papers. en https://siliconandsystems.com/en/articles/nvhbm-base-die/ https://siliconandsystems.com/en/articles/nvhbm-base-die/ Thu, 03 Sep 2026 18:53:05 GMT NVIDIA moved its custom memory controller from the XPU compute die into the HBM base die. The disclosed area, bandwidth and power gains are promising, but they are architectural targets with different denominators, not measurements from shipping silicon. https://siliconandsystems.com/en/articles/cerebras-cs4-nexus/ https://siliconandsystems.com/en/articles/cerebras-cs4-nexus/ Sat, 05 Sep 2026 09:09:38 GMT CS-4 combines three WSE-3T systems in the modular Nexus rack and advertises 160.5 PB/s of aggregate compute-fabric bandwidth. Its real proposition is serviceable wafer-scale inference, while the headline speed remains vendor-tested. https://siliconandsystems.com/en/articles/lpddr-servers/ https://siliconandsystems.com/en/articles/lpddr-servers/ Tue, 25 Aug 2026 15:00:00 GMT In six months, mobile-derived memory produced working LPDDR6 silicon, reached 1.5 TB and 1.2 TB/s beside NVIDIA's Vera CPU in serviceable modules, and moved computation into DRAM banks. The common constraint is power. https://siliconandsystems.com/en/articles/openai-jalapeno-inference/ https://siliconandsystems.com/en/articles/openai-jalapeno-inference/ Tue, 01 Sep 2026 11:01:38 GMT OpenAI's Jalapeño keeps changing inference phases on one locality-first ASIC instead of moving KV state among specialized devices. Its Hot Chips results are strongest at low latency, but the comparison still stops at package-TDP normalization and vendor-run systems. https://siliconandsystems.com/en/articles/amd-mi400-helios/ https://siliconandsystems.com/en/articles/amd-mi400-helios/ Sat, 05 Sep 2026 09:09:39 GMT MI455X supplies 432 GB of HBM4 and 23.3 TB/s per GPU, but Helios is designed around repeatable four-GPU trays and a one-hop 72-GPU UALoE domain. The open interfaces do not remove rack integration risk. https://siliconandsystems.com/en/articles/ibm-z-arm-dual-architecture/ https://siliconandsystems.com/en/articles/ibm-z-arm-dual-architecture/ Sat, 05 Sep 2026 09:09:37 GMT IBM is designing each 2 nm core to execute IBM Z and Arm instructions rather than assigning the two ISAs to separate core pools. The architectural gain is software placement inside one reliability and I/O domain, not a benchmark result. https://siliconandsystems.com/en/articles/industry-memory-storage-2026/ https://siliconandsystems.com/en/articles/industry-memory-storage-2026/ Sat, 29 Aug 2026 15:00:00 GMT Through August 30, 52 company-affiliated records connect HBM4, LPDDR6, vertical DRAM, zoned UFS, AI I/O, tape, object storage, SSD reliability, and cloud data placement. https://siliconandsystems.com/en/articles/intel-agentic-ai-silicon/ https://siliconandsystems.com/en/articles/intel-agentic-ai-silicon/ Sat, 05 Sep 2026 09:09:42 GMT Diamond Rapids, Crescent Island and Wildcat Lake place orchestration, inference and edge execution in different silicon and power envelopes. Intel’s common thread is 18A, UCIe and Foveros, not one universal agentic-AI processor. https://siliconandsystems.com/en/articles/vera-cpu-memory-balance/ https://siliconandsystems.com/en/articles/vera-cpu-memory-balance/ Fri, 28 Aug 2026 15:00:00 GMT NVIDIA's Vera CPU pairs 88 wide Olympus cores with 164 MB of shared cache and a peak 1.2 TB/s from serviceable LPDDR5X modules. The architecture is aimed at agentic workloads that alternate serial control, irregular memory access and accelerator handoffs. Its most revealing number is 12.7 GB/s per core, but the evidence remains vendor-authored. https://siliconandsystems.com/en/articles/tencent-pegasus-fabric/ https://siliconandsystems.com/en/articles/tencent-pegasus-fabric/ Sun, 30 Aug 2026 11:27:42 GMT Pegasus separates DPU control from the RDMA data path and offloads packet spraying plus credit control to RNICs. Tencent reports two years of production use across 8,000 GPUs. https://siliconandsystems.com/en/articles/cxl-onechip/ https://siliconandsystems.com/en/articles/cxl-onechip/ Sat, 29 Aug 2026 15:00:00 GMT NVLink provides a fast local domain, while Ethernet or InfiniBand connects those domains through a scale-out network boundary. This review examines how CXL can extend shared addressing, transaction ordering, and device-level recovery across the datacenter. https://siliconandsystems.com/en/articles/burst-aware-congestion-evaluation/ https://siliconandsystems.com/en/articles/burst-aware-congestion-evaluation/ Sun, 30 Aug 2026 01:49:33 GMT A Meta and Carnegie Mellon study finds that common synthetic datacenter workloads reproduce burst occurrence but not production burst clustering. Four dimensions turn congestion-control testing into a coverage problem. https://siliconandsystems.com/en/articles/hbf/ https://siliconandsystems.com/en/articles/hbf/ Tue, 25 Aug 2026 15:00:00 GMT Frontier models outgrew a GPU's HBM years ago, and the standard fix has been buying more GPUs. A specification released through the Open Compute Project on August 3 defines another path: NAND stacked like HBM, 512 GB per stack at up to 3 TB/s, with Google and Tenstorrent already at the table. We read the spec, and the fine print about writes. https://siliconandsystems.com/en/articles/ai-rtl-closed-loop/ https://siliconandsystems.com/en/articles/ai-rtl-closed-loop/ Mon, 31 Aug 2026 05:40:54 GMT StepPRM-RTL, Spec2RTL-Agent, ScaleRTL, and ASPEN show why useful RTL automation is a verified search loop rather than a single prompt that emits Verilog. https://siliconandsystems.com/en/articles/industry-circuits-2026/ https://siliconandsystems.com/en/articles/industry-circuits-2026/ Sat, 29 Aug 2026 15:00:00 GMT Ten public industry papers through August 2026 connect measured gains to structure in phased arrays, PLLs, data conversion, MEMS drive, and edge learning. https://siliconandsystems.com/en/articles/ai-infrastructure-runtime-2025-2026/ https://siliconandsystems.com/en/articles/ai-infrastructure-runtime-2025-2026/ Thu, 27 Aug 2026 15:00:00 GMT Nine industry papers from 2025 and 2026 show the same architectural shift across power, cooling, fabrics, storage, serving, agent workflows, RL post-training, fleet scheduling and recovery: the datacenter itself is becoming a programmable runtime. https://siliconandsystems.com/en/articles/ant-serverless-batch/ https://siliconandsystems.com/en/articles/ant-serverless-batch/ Mon, 31 Aug 2026 16:50:27 GMT Ant Group's Quark applies serverless allocation and fast instances to reclaim slot, gap, start, and stop idle in colocated Spark workloads. https://siliconandsystems.com/en/articles/asi-gpu-fleet/ https://siliconandsystems.com/en/articles/asi-gpu-fleet/ Wed, 26 Aug 2026 15:00:00 GMT A six-month trace from Alibaba's 155,410-GPU shared fleet shows why idle capacity can still reject a job. Exact model requests, CPU ratios and network locality reshape scheduling, while defragmentation and opportunistic work raise useful allocation from 68% to 93%. https://siliconandsystems.com/en/articles/blink-flat-workload-profiling/ https://siliconandsystems.com/en/articles/blink-flat-workload-profiling/ Mon, 31 Aug 2026 16:50:27 GMT Blink replaces biased PMU sampling with bounded function instrumentation when mobile workloads have no dominant hotspot. https://siliconandsystems.com/en/articles/bodega-roster-leases/ https://siliconandsystems.com/en/articles/bodega-roster-leases/ Mon, 31 Aug 2026 16:50:27 GMT Bodega generalizes leadership into leased responder rosters so selected replicas can answer local linearizable reads despite writes. https://siliconandsystems.com/en/articles/bytedance-llm-data-pipeline/ https://siliconandsystems.com/en/articles/bytedance-llm-data-pipeline/ Mon, 31 Aug 2026 16:50:27 GMT ByteDance turns deterministic training progress into checkpoint replication, hot-file fanout, and storage-side multimodal transformation for its existing HDFS fleet. https://siliconandsystems.com/en/articles/diting-cloud-observability/ https://siliconandsystems.com/en/articles/diting-cloud-observability/ Mon, 31 Aug 2026 16:50:27 GMT Alibaba's DiTing centralizes telemetry persistence and harvests spare compute for ingestion and queries. https://siliconandsystems.com/en/articles/dvla-vm-lifetime-scheduling/ https://siliconandsystems.com/en/articles/dvla-vm-lifetime-scheduling/ Mon, 31 Aug 2026 16:50:27 GMT Alibaba Cloud's DVLA predicts lifetime at several horizons, prevents long-lived VM scatter, and repays accumulated placement debt through migration. https://siliconandsystems.com/en/articles/dynarl-rl-scheduling/ https://siliconandsystems.com/en/articles/dynarl-rl-scheduling/ Mon, 31 Aug 2026 16:50:27 GMT DynaRL moves GPUs among rollout, inference, tools, and training as their bottlenecks change within one reinforcement-learning iteration. https://siliconandsystems.com/en/articles/eco-code-efficiency/ https://siliconandsystems.com/en/articles/eco-code-efficiency/ Mon, 31 Aug 2026 16:50:27 GMT Google's ECO combines fleet profiles, historical optimizations, LLM edits, tests, human review, and production monitoring into one efficiency pipeline. https://siliconandsystems.com/en/articles/gpu-silent-errors/ https://siliconandsystems.com/en/articles/gpu-silent-errors/ Wed, 26 Aug 2026 15:00:00 GMT Three ByteDance OSDI 2026 papers divide silent-error operations into online detection, workload-faithful hardware isolation, and operator-level debugging. Together they cover 35 million GPU-hours, 40 mitigated incidents, and more than 20 diagnosed production issues. https://siliconandsystems.com/en/articles/helmsman-anns-clustering/ https://siliconandsystems.com/en/articles/helmsman-anns-clustering/ Mon, 31 Aug 2026 16:50:27 GMT Helmsman combines userspace NVMe I/O, learned pruning, and GPU index construction to replace a large in-DRAM ANNS fleet. https://siliconandsystems.com/en/articles/hyperscale-power-lifecycle/ https://siliconandsystems.com/en/articles/hyperscale-power-lifecycle/ Mon, 31 Aug 2026 16:50:27 GMT Meta combines production telemetry for mature servers with counter-based PowerSight estimates before new hardware has power sensors at scale. https://siliconandsystems.com/en/articles/iland-ios-instrumentation/ https://siliconandsystems.com/en/articles/iland-ios-instrumentation/ Mon, 31 Aug 2026 16:50:27 GMT iLand interprets app instructions through precompiled micro-operations while native iOS libraries handle UI and media, enabling sandboxed dynamic instrumentation without JIT or jailbreak. https://siliconandsystems.com/en/articles/inside-out-vm-introspection/ https://siliconandsystems.com/en/articles/inside-out-vm-introspection/ Mon, 31 Aug 2026 16:50:27 GMT GOODKIT maps selected target memory into lightweight observer VMs, avoiding pause-heavy introspection while keeping observers isolated. https://siliconandsystems.com/en/articles/janus-nested-virtualization/ https://siliconandsystems.com/en/articles/janus-nested-virtualization/ Mon, 31 Aug 2026 16:50:27 GMT JANUS keeps CPU world switches in the guest hypervisor while the host owns memory translation for secure containers inside cloud VMs. https://siliconandsystems.com/en/articles/jwmalloc-verified-allocator/ https://siliconandsystems.com/en/articles/jwmalloc-verified-allocator/ Mon, 31 Aug 2026 16:50:27 GMT Huawei's jwmalloc combines cross-size slab reuse, fragment indexing, lifetime-guided reclamation, and weak-memory verification for mobile devices. https://siliconandsystems.com/en/articles/logdrive-shared-logs/ https://siliconandsystems.com/en/articles/logdrive-shared-logs/ Mon, 31 Aug 2026 16:50:27 GMT Confluent's LogDrive composes cloud stores for durability while AtomicLog adds ordering, cutting metadata cost for an S3 pub-sub service. https://siliconandsystems.com/en/articles/mdk-memory-reclamation/ https://siliconandsystems.com/en/articles/mdk-memory-reclamation/ Mon, 31 Aug 2026 16:50:27 GMT MDK replaces miss-ratio curves with performance-constrained memory-saving curves, giving proactive datacenter reclaimers an offline optimum and faster policy evaluation. https://siliconandsystems.com/en/articles/mobile-cpu-scheduling-trinity/ https://siliconandsystems.com/en/articles/mobile-cpu-scheduling-trinity/ Mon, 31 Aug 2026 16:50:27 GMT Honor's MUSCHED propagates interaction urgency through IPC, adds a VIP class, and loads eBPF scheduling policy without rebuilding the kernel. https://siliconandsystems.com/en/articles/murakkab-agent-orchestration/ https://siliconandsystems.com/en/articles/murakkab-agent-orchestration/ Fri, 28 Aug 2026 15:00:00 GMT Murakkab exposes agent tasks and dependencies to one SLO-aware control plane. Across the evaluated Azure-derived workloads, joint workflow and resource optimization cuts GPUs, energy, and cost without treating every model call as an independent service. https://siliconandsystems.com/en/articles/obase-memory-tiering/ https://siliconandsystems.com/en/articles/obase-memory-tiering/ Mon, 31 Aug 2026 16:50:27 GMT OBASE reorganizes movable objects by access temperature so existing page-level reclaimers see uniformly hot and cold pages instead of fragmented mixtures. https://siliconandsystems.com/en/articles/pims-datacenter-maintenance/ https://siliconandsystems.com/en/articles/pims-datacenter-maintenance/ Mon, 31 Aug 2026 16:50:27 GMT Meta's PIMS aligns maintenance, placement, contracts, and priorities around fault domains to shrink reserve capacity while keeping rollout deadlines. https://siliconandsystems.com/en/articles/quota-marketplace-ml-training/ https://siliconandsystems.com/en/articles/quota-marketplace-ml-training/ Mon, 31 Aug 2026 16:50:27 GMT Google's Quota Marketplace prices heterogeneous accelerator demand across business pools. https://siliconandsystems.com/en/articles/ramryder-elastic-memory/ https://siliconandsystems.com/en/articles/ramryder-elastic-memory/ Tue, 08 Sep 2026 15:22:20 GMT RamRyder exposes DRAM channels to a modified virtualization stack, separating baseline isolation from elastic CXL resources. Its benefit depends on page placement, not simply attaching more memory. https://siliconandsystems.com/en/articles/sdchunter-gpu-replay/ https://siliconandsystems.com/en/articles/sdchunter-gpu-replay/ Mon, 31 Aug 2026 16:50:27 GMT SDCHUNTER uses deterministic kernels and tensor signatures to distinguish silent GPU corruption from ordinary LLM training noise. https://siliconandsystems.com/en/articles/seer-synchronous-rl/ https://siliconandsystems.com/en/articles/seer-synchronous-rl/ Mon, 31 Aug 2026 16:50:27 GMT SEER uses prompt-group context, divided rollout, a global KV pool, and adaptive speculative decoding to shorten synchronous RL tails. https://siliconandsystems.com/en/articles/stateful-service-fidelity-models/ https://siliconandsystems.com/en/articles/stateful-service-fidelity-models/ Mon, 31 Aug 2026 16:50:27 GMT AWS combines executable models, predicate abstraction, and systematic tests to preserve S3 API behavior. https://siliconandsystems.com/en/articles/strata-kv-cache/ https://siliconandsystems.com/en/articles/strata-kv-cache/ Fri, 28 Aug 2026 15:00:00 GMT Strata treats CPU-to-GPU bandwidth and KV-cache readiness as schedulable resources. GPU-assisted transfers and cache-aware batching raise long-context serving throughput by up to 5× in the evaluated cases. https://siliconandsystems.com/en/articles/striatrace/ https://siliconandsystems.com/en/articles/striatrace/ Wed, 26 Aug 2026 15:00:00 GMT Alibaba's StriaTrace instruments synchronization points and critical paths continuously, then collects detail only around an anomaly. It keeps tracing overhead below 1% across 1,700 production instances serving more than 180 million requests per day. https://siliconandsystems.com/en/articles/tessera-qwen/ https://siliconandsystems.com/en/articles/tessera-qwen/ Wed, 26 Aug 2026 15:00:00 GMT Alibaba's Tessera treats heterogeneous Qwen layers, communication overlap, and runtime routing bubbles as one pipeline-planning problem. Across five production workloads on 4,096 to 12,288 GPUs, it raises throughput by 20% to 33%. https://siliconandsystems.com/en/articles/trainmover/ https://siliconandsystems.com/en/articles/trainmover/ Wed, 26 Aug 2026 15:00:00 GMT Alibaba's TrainMover replaces one machine without rebuilding every communication group or warming it inside the live job. Expected interruptions stay below 20 seconds and unexpected failures below 30 seconds at 1,024 GPUs. https://siliconandsystems.com/en/articles/weave-rl-coscheduling/ https://siliconandsystems.com/en/articles/weave-rl-coscheduling/ Fri, 28 Aug 2026 15:00:00 GMT Weave preserves synchronous on-policy learning while filling one job's dependency bubbles with another job's active phase. A two-week replay cuts provisioning cost by 1.84× against isolated disaggregation. https://siliconandsystems.com/en/articles/xkernel-kernel-tunability/ https://siliconandsystems.com/en/articles/xkernel-kernel-tunability/ Mon, 31 Aug 2026 16:50:27 GMT Xkernel rewrites the state around compile-time Linux performance constants so production policy can change them without a reboot. https://siliconandsystems.com/en/articles/ampereone-memory-tagging/ https://siliconandsystems.com/en/articles/ampereone-memory-tagging/ Sat, 29 Aug 2026 15:00:00 GMT AmpereOne is the first datacenter CPU with Arm Memory Tagging Extension support. It co-locates allocation tags with protected data, avoiding reserved-DRAM capacity loss and keeping synchronous checks to a single-digit slowdown. https://siliconandsystems.com/en/articles/m100-dataflow/ https://siliconandsystems.com/en/articles/m100-dataflow/ Sat, 29 Aug 2026 15:00:00 GMT Li Auto's M100 uses compiler-orchestrated tensor dataflow for autonomous driving and LLM inference. At equal power and DDR bandwidth, it reports 3.8× the UniAD frame rate of NVIDIA Thor-U. https://siliconandsystems.com/en/articles/pbr-cxl/ https://siliconandsystems.com/en/articles/pbr-cxl/ Tue, 25 Aug 2026 15:00:00 GMT Commercial CXL memory expanders answer in 265 to 442 ns, and a switch hop raises that latency by roughly 2×. A Panmnesia paper at ISCA 2026 traces the overhead to PCIe-derived controller silicon and answers with a 4 nm chip: a unified controller below 50 ns round trip, and a port-based routing switch evaluated to 64 nodes. https://siliconandsystems.com/en/articles/prometheus-cooling/ https://siliconandsystems.com/en/articles/prometheus-cooling/ Wed, 26 Aug 2026 15:00:00 GMT Google's Prometheus study combines historical observations with climate projections across 30 datacenters. The result is an 11% average cooling-capacity increase, a 48% worst case and a new operating plan for heat that exceeds the design file. https://siliconandsystems.com/en/articles/raptor-3dimc/ https://siliconandsystems.com/en/articles/raptor-3dimc/ Tue, 25 Aug 2026 15:00:00 GMT HBM keeps memory millimeters from compute and pays a PHY toll on every bit. At Hot Chips 2026, d-Matrix showed early silicon that shrinks the distance to microns: a 4 nm compute die bonded face to face onto custom DRAM, delivering 100 TB/s from a 32 GB card at 0.37 pJ/bit. The catch sits in the capacity column. https://siliconandsystems.com/en/articles/sigries-rowhammer/ https://siliconandsystems.com/en/articles/sigries-rowhammer/ Sat, 29 Aug 2026 15:00:00 GMT Sigries combines small Misra-Gries counter tables with row sampling and is implemented in Azure Cobalt 200. Benign traces stay in a zero-DRAM-bandwidth light mode; only stressed sub-banks enter the heavier defense. https://siliconandsystems.com/en/articles/vistara-cxl/ https://siliconandsystems.com/en/articles/vistara-cxl/ Mon, 24 Aug 2026 15:00:00 GMT Roughly 40% of the servers in Meta's fleet are memory-capacity bound. A paper presented at ISCA 2026 reports the first end-to-end CXL deployment at hyperscale: a custom ASIC that turns DDR4 from decommissioned servers into an expansion tier, and the production numbers behind it. https://siliconandsystems.com/en/articles/samsung-3d-stacked-fet/ https://siliconandsystems.com/en/articles/samsung-3d-stacked-fet/ Sun, 30 Aug 2026 11:27:42 GMT Samsung's VLSI 2026 paper puts triple-nanosheet nFETs above triple-nanosheet pFETs at a 42 nm gate pitch. The result is a process-integration milestone, not yet a dense logic product. https://siliconandsystems.com/en/articles/industry-architecture-isca-2026/ https://siliconandsystems.com/en/articles/industry-architecture-isca-2026/ Mon, 31 Aug 2026 13:51:06 GMT 43 verified company-affiliated ISCA papers, including Panmnesia's CXL controller and routing switch, connect architecture mechanisms to production software, memory behavior, reliability, and fleet operation. https://siliconandsystems.com/en/articles/power-cluster-150mw/ https://siliconandsystems.com/en/articles/power-cluster-150mw/ Wed, 26 Aug 2026 15:00:00 GMT Meta's 150 MW GB200 deployment shows why AI capacity is decided at the breaker, not the GPU nameplate. A lower device limit, calibrated telemetry and coordinated runtime controls raise cluster throughput by about 14%. https://siliconandsystems.com/en/articles/reasoning-inference-capacity/ https://siliconandsystems.com/en/articles/reasoning-inference-capacity/ Sat, 29 Aug 2026 15:00:00 GMT Micron and Argonne characterize reasoning inference from 8B to 671B parameters. Long outputs fill KV cache, leave memory stranded under data parallelism, and make tensor parallelism useful near the 32B crossover. https://siliconandsystems.com/en/articles/meta-llm-deployment-search/ https://siliconandsystems.com/en/articles/meta-llm-deployment-search/ Sat, 05 Sep 2026 15:00:00 GMT Meta's MLSys 2026 industry paper treats LLM deployment as a constrained search over hardware, parallelism, runtime, workload, and latency. A benchmark-driven simulator turns millions of combinations into phase-specific decisions for online, offline, dense, and MoE inference. https://siliconandsystems.com/en/articles/agentix-program-serving/ https://siliconandsystems.com/en/articles/agentix-program-serving/ Tue, 08 Sep 2026 15:22:20 GMT Agentix carries program history into LLM scheduling so repeated calls do not continually regain priority. Its gains concern completed agent programs, not a faster matrix kernel. https://siliconandsystems.com/en/articles/burst-soft-rdma/ https://siliconandsystems.com/en/articles/burst-soft-rdma/ Tue, 08 Sep 2026 15:22:20 GMT BURST implements a RoCE-compatible transport in a userspace service so ordinary Ethernet endpoints can communicate with RNICs. Near-400G throughput needs parallel queues, and faster KV transfer is not the same as faster end-to-end inference. https://siliconandsystems.com/en/articles/cloud-block-tail-latency/ https://siliconandsystems.com/en/articles/cloud-block-tail-latency/ Tue, 08 Sep 2026 15:22:20 GMT Alibaba's block store still suffered long tails after spreading traffic evenly. Segment-level burst admission and I/O-aware event scheduling address two different reasons that a quiet request can wait. https://siliconandsystems.com/en/articles/droidspeak-cross-model-kv/ https://siliconandsystems.com/en/articles/droidspeak-cross-model-kv/ Tue, 08 Sep 2026 15:22:20 GMT DroidSpeak replaces part of a model's prefill with state computed by a related model. Selective layer recomputation preserves measured task quality, but this is approximate reuse, not ordinary lossless prefix caching. https://siliconandsystems.com/en/articles/eroica-gpu-troubleshooting/ https://siliconandsystems.com/en/articles/eroica-gpu-troubleshooting/ Sun, 06 Sep 2026 15:20:45 GMT EROICA compresses fine-grained execution profiles into comparable behavior signatures, then uses differences across workers to locate hardware and software slowdowns without tracing an entire GPU fleet. https://siliconandsystems.com/en/articles/falconfs-training-files/ https://siliconandsystems.com/en/articles/falconfs-training-files/ Tue, 08 Sep 2026 15:22:20 GMT Huawei and SJTU's FalconFS targets the metadata work behind random small-file access. Replicating directory information on servers lets training clients avoid maintaining a large directory cache. https://siliconandsystems.com/en/articles/flexllm-token-coserving/ https://siliconandsystems.com/en/articles/flexllm-token-coserving/ Sun, 06 Sep 2026 15:20:49 GMT FlexLLM compiles parameter-efficient fine-tuning to share a base model, then interleaves inference and training tokens inside each iteration while protecting inference latency SLOs. https://siliconandsystems.com/en/articles/matryoshka-network-compiler/ https://siliconandsystems.com/en/articles/matryoshka-network-compiler/ Sun, 30 Aug 2026 01:49:33 GMT Meta's Matryoshka compiles network intent into validated switch state across nearly 900 datacenter networks. The 100K-GPU case shows why topology reuse, deterministic generation, and staged validation now belong in the fabric architecture. https://siliconandsystems.com/en/articles/meta-matryoshka/ https://siliconandsystems.com/en/articles/meta-matryoshka/ Sun, 30 Aug 2026 11:27:42 GMT Matryoshka compiles topology, addressing and routing intent into validated switch configurations. Meta reports six years of use across nearly 900 datacenter networks and 18 network types. https://siliconandsystems.com/en/articles/octopus-cxl-pod/ https://siliconandsystems.com/en/articles/octopus-cxl-pod/ Sun, 30 Aug 2026 23:48:25 GMT Microsoft Azure and university researchers replace the fully connected CXL pod with sparse, four-port memory devices. A three-server prototype and a 96-server model show why topology, cable length and workload placement decide whether pooling saves money. https://siliconandsystems.com/en/articles/sonic-dash-smartswitch/ https://siliconandsystems.com/en/articles/sonic-dash-smartswitch/ Tue, 08 Sep 2026 15:22:20 GMT SONiC DASH integrates a pool of DPUs into Azure's T1 switches. Its contribution is as much about bounded service semantics and deployable capacity as it is about packet throughput. https://siliconandsystems.com/en/articles/spec-cpu-2026/ https://siliconandsystems.com/en/articles/spec-cpu-2026/ Sat, 29 Aug 2026 15:00:00 GMT SPEC CPU 2026 expands to 52 components and introduces Rolling Round-Robin Rate, where cores rotate through different programs. The method gives heterogeneous multiprogrammed CPU research a common workload construction. https://siliconandsystems.com/en/articles/adaserve-multi-slo-speculation/ https://siliconandsystems.com/en/articles/adaserve-multi-slo-speculation/ Sun, 06 Sep 2026 15:20:52 GMT AdaServe converts each request's latency objective into a hardware-aware speculative-decoding tree, then separates speculation, selection, and verification to serve mixed SLOs efficiently. https://siliconandsystems.com/en/articles/ibp-lossless-gpu-compression/ https://siliconandsystems.com/en/articles/ibp-lossless-gpu-compression/ Sun, 06 Sep 2026 15:20:53 GMT Invariant Bit Packing removes bit positions shared by groups of tensors, then reconstructs them on the GPU to reduce host-to-device traffic without quantization error. https://siliconandsystems.com/en/articles/mpccs-dual-network-collectives/ https://siliconandsystems.com/en/articles/mpccs-dual-network-collectives/ Sun, 06 Sep 2026 15:20:46 GMT MPCCS sends one collective over both the accelerator scale-up fabric and the cloud scale-out network, adapting the split with measured bandwidth-delay product and coflow synchronization. https://siliconandsystems.com/en/articles/google-tpu8/ https://siliconandsystems.com/en/articles/google-tpu8/ Tue, 01 Sep 2026 21:59:47 GMT Google's TPU 8t widens the training fabric while TPU 8i shortens serving collectives. The split moves specialization from the matrix unit into memory, topology, hosts and software. https://siliconandsystems.com/en/articles/arm-agi-cpu/ https://siliconandsystems.com/en/articles/arm-agi-cpu/ Sat, 05 Sep 2026 09:09:41 GMT Arm AGI CPU pairs up to 136 Neoverse V3 cores with 12 DDR5 channels and a 300 W envelope, then supplies a dual-node 1OU reference server. The strategic change is ownership of the deployable platform boundary. https://siliconandsystems.com/en/articles/hana-cxl-memory-pool/ https://siliconandsystems.com/en/articles/hana-cxl-memory-pool/ Sun, 30 Aug 2026 23:48:25 GMT SAP and Samsung test dynamic CXL pooled memory with an XConn switch, Samsung CMM-D cards and enterprise HANA workloads. The result is a placement rule, not a universal speed claim: sequential and temporary data can move, while random operational heaps should remain local. https://siliconandsystems.com/en/articles/gpu-cloud-lottery/ https://siliconandsystems.com/en/articles/gpu-cloud-lottery/ Sun, 30 Aug 2026 11:16:52 GMT A GPGPU 2026 industry study measured 3,534 physical GPUs across 11 clouds and found that identical model names can conceal double-digit performance ranges. The purchasing question is therefore a distribution, not a peak specification. https://siliconandsystems.com/en/articles/industry-architecture-asplos-2026/ https://siliconandsystems.com/en/articles/industry-architecture-asplos-2026/ Mon, 31 Aug 2026 13:51:02 GMT 44 verified company-affiliated ASPLOS papers connect architecture mechanisms to production software, model execution, memory behavior, reliability, and fleet operation. https://siliconandsystems.com/en/articles/acos-object-store/ https://siliconandsystems.com/en/articles/acos-object-store/ Sun, 30 Aug 2026 01:10:21 GMT ACOS moved from two complete regional copies to a five-region XOR code while preserving local repair. The production migration shows where capacity savings become latency and failure-management work. https://siliconandsystems.com/en/articles/aiturbo-grouped-io/ https://siliconandsystems.com/en/articles/aiturbo-grouped-io/ Fri, 28 Aug 2026 15:00:00 GMT AITURBO lets cloud storage see which accelerators are reading or writing together. That one semantic change enables transparent deduplication, host-DRAM staging and compute-fabric broadcast without rebuilding every AI framework. https://siliconandsystems.com/en/articles/bytedance-discard-gc/ https://siliconandsystems.com/en/articles/bytedance-discard-gc/ Mon, 31 Aug 2026 16:50:27 GMT ByteDance's DisCoGC coordinates discard and compaction across a layered log store, reclaiming large invalid ranges without copying every surviving byte. https://siliconandsystems.com/en/articles/cacheslide-kv-cache/ https://siliconandsystems.com/en/articles/cacheslide-kv-cache/ Sun, 30 Aug 2026 02:19:01 GMT Agent prompts keep stable segments but move their absolute token positions. CacheSlide aligns those segments, repairs selected cross-attention, and manages the resulting KV-cache spill path. https://siliconandsystems.com/en/articles/cloud-local-storage/ https://siliconandsystems.com/en/articles/cloud-local-storage/ Sat, 29 Aug 2026 15:00:00 GMT Alibaba's production history shows why cloud-local NVMe moved from a kernel stack to polling, then to DPU offload and an ASIC-SoC design before adding remote durability as a hybrid tier. https://siliconandsystems.com/en/articles/cofs-container-startup/ https://siliconandsystems.com/en/articles/cofs-container-startup/ Mon, 31 Aug 2026 16:50:27 GMT CoFS moves fixed container-image metadata into minimal perfect hashes and cached payloads into the host kernel, reducing lookup work without keeping every read on a userspace FUSE path. https://siliconandsystems.com/en/articles/failureminer-ssd-failures/ https://siliconandsystems.com/en/articles/failureminer-ssd-failures/ Mon, 31 Aug 2026 16:50:27 GMT FailureMiner preserves healthy samples near the failure boundary and compresses a random forest into a few joint telemetry decisions that operators can act on. https://siliconandsystems.com/en/articles/linux-data-integrity/ https://siliconandsystems.com/en/articles/linux-data-integrity/ Mon, 31 Aug 2026 16:50:27 GMT Linux FS-PI lets applications and filesystems carry protection metadata to capable drives, adding checksums to XFS and removing BTRFS's separate checksum-tree traffic. https://siliconandsystems.com/en/articles/polarstore-cloud-database-compression/ https://siliconandsystems.com/en/articles/polarstore-cloud-database-compression/ Mon, 31 Aug 2026 16:50:27 GMT PolarStore combines computational-storage compression with adaptive software codecs, then bypasses or reshapes the database I/O paths where compression would delay commits and reads. https://siliconandsystems.com/en/articles/programmable-page-cache-model-loading/ https://siliconandsystems.com/en/articles/programmable-page-cache-model-loading/ Sun, 30 Aug 2026 01:48:21 GMT PPC makes the kernel page-cache policy programmable without changing the inference framework. MAIO then uses repeatable model-loading traces to prefetch, place, and evict pages around each accelerator. https://siliconandsystems.com/en/articles/skysync-file-synchronization/ https://siliconandsystems.com/en/articles/skysync-file-synchronization/ Mon, 31 Aug 2026 16:50:27 GMT SkySync derives rsync- and dsync-compatible deltas from storage checksums, cutting repeated computation without reducing the bytes required to represent a file change. https://siliconandsystems.com/en/articles/sorted-compressed-filesystem/ https://siliconandsystems.com/en/articles/sorted-compressed-filesystem/ Sun, 30 Aug 2026 01:10:21 GMT RubikFS rearranges similar and frequently read chunks before block compression. Across six images, that placement decision improves density while reducing the extra reads caused by large compressed blocks. https://siliconandsystems.com/en/articles/tape-archive-cloud/ https://siliconandsystems.com/en/articles/tape-archive-cloud/ Sat, 29 Aug 2026 15:00:00 GMT Huawei Cloud's TapeOBS turns an hours-level restore promise into scheduling freedom, batching writes, erasure coding, and restores around the physical limits of tape libraries. https://siliconandsystems.com/en/articles/zoned-ufs-mobile-storage/ https://siliconandsystems.com/en/articles/zoned-ufs-mobile-storage/ Mon, 31 Aug 2026 16:50:27 GMT A commercial Zoned UFS stack coordinates F2FS, Linux ordering, controller SRAM, and background reclamation to keep mobile flash predictable as devices age. https://siliconandsystems.com/en/articles/ai-eda-commercial-tapeouts/ https://siliconandsystems.com/en/articles/ai-eda-commercial-tapeouts/ Mon, 31 Aug 2026 05:44:42 GMT Synopsys and Cadence report hundreds to more than one thousand AI-assisted tapeouts, with named cases at Samsung, STMicroelectronics, SK hynix, MediaTek and Renesas. The evidence supports scaled design-space search, not autonomous chip creation. https://siliconandsystems.com/en/articles/coherent-cpo-direct-drive/ https://siliconandsystems.com/en/articles/coherent-cpo-direct-drive/ Sun, 30 Aug 2026 23:53:10 GMT A 45 nm CMOS-SOI transmitter reaches 212 Gb/s 16-QAM with a 400 µm direct-driven modulator. The result changes the energy and area boundary for coherent co-packaged optics, but not yet the yield or thermal proof. https://siliconandsystems.com/en/articles/ai-eda-recipe-transfer/ https://siliconandsystems.com/en/articles/ai-eda-recipe-transfer/ Mon, 31 Aug 2026 05:40:50 GMT InsightAlign and FastTuner turn previous physical-design runs into ranked recipes and transferable policies, reducing the cold start on each new block. https://siliconandsystems.com/en/articles/industry-architecture-hpca-2026/ https://siliconandsystems.com/en/articles/industry-architecture-hpca-2026/ Mon, 31 Aug 2026 13:51:04 GMT 28 verified company-affiliated HPCA papers connect architecture mechanisms to production software, model execution, memory behavior, reliability, and fleet operation. https://siliconandsystems.com/en/articles/ualink-landscape/ https://siliconandsystems.com/en/articles/ualink-landscape/ Tue, 25 Aug 2026 15:00:00 GMT The scale-up rack has four would-be landlords. This review reads UALink against NVLink, Ethernet and Huawei's Unified Bus, then updates the map for UALink Common 2.0 and the released ESUN 1.0 specification. https://siliconandsystems.com/en/articles/maia-200-ethernet-scaleup/ https://siliconandsystems.com/en/articles/maia-200-ethernet-scaleup/ Sat, 05 Sep 2026 09:09:40 GMT Maia 200 combines 216 GB HBM3e, 272 MB SRAM and 2.8 TB/s of dedicated scale-up bandwidth with a two-tier Ethernet design. Microsoft controls the chip, transport and fleet, so the architecture is as much an operating model as a device. https://siliconandsystems.com/en/articles/ai-pnr-objectives/ https://siliconandsystems.com/en/articles/ai-pnr-objectives/ Mon, 31 Aug 2026 05:40:51 GMT C3PO, DCO-3D, and reinforcement-learning routing show how AI connects timing, congestion, wirelength, and local repair without replacing the implementation flow. https://siliconandsystems.com/en/articles/kernelevolve/ https://siliconandsystems.com/en/articles/kernelevolve/ Sat, 29 Aug 2026 15:00:00 GMT KernelEvolve searches, compiles, runs, and remembers accelerator kernels across NVIDIA, AMD, and MTIA. Meta reports 480/480 correct operator-platform pairs and production speedups from 1.25× to 17×. https://siliconandsystems.com/en/articles/neocloud-evidence/ https://siliconandsystems.com/en/articles/neocloud-evidence/ Wed, 26 Aug 2026 15:00:00 GMT CoreWeave publishes link-readiness and storage benchmarks, Nebius reports customer-cluster MTBF and recovery time, and Lambda describes a portable operating stack. The difference is not a vendor ranking but an evidence map for AI-cloud buyers. https://siliconandsystems.com/en/articles/tsmc-cfet-circuits/ https://siliconandsystems.com/en/articles/tsmc-cfet-circuits/ Sun, 30 Aug 2026 11:27:42 GMT TSMC's IEDM 2025 paper moves monolithic CFET from isolated transistors into a 101-stage ring oscillator and operational 6T SRAM cells below a 48 nm gate pitch. https://siliconandsystems.com/en/articles/beluga-cxl/ https://siliconandsystems.com/en/articles/beluga-cxl/ Mon, 24 Aug 2026 15:00:00 GMT A 50M-token KVCache needs about 20 TB of DRAM, and RDMA memory pools pay for that capacity in synchronization and programming complexity. Alibaba Cloud's Beluga puts the first commercial CXL 2.0 switch under vLLM, letting GPUs load and store into a shared 8 TB pool and cutting time-to-first-token by 89.6%. https://siliconandsystems.com/en/articles/ai-architecture-contract/ https://siliconandsystems.com/en/articles/ai-architecture-contract/ Mon, 31 Aug 2026 05:40:53 GMT QiMeng-CPU-v2, LEMOE, and multimodal SoC DSE show how AI narrows architecture choices, and why executable behavior remains the evidence boundary. https://siliconandsystems.com/en/articles/evatec-pvd-warpage-hybrid-bonding/ https://siliconandsystems.com/en/articles/evatec-pvd-warpage-hybrid-bonding/ Sun, 30 Aug 2026 23:57:41 GMT Evatec proposes low-temperature PVD SiCN for hybrid-bond interfaces and stressed SiN or SiON films for wafer-flatness control. The process claims up to 1,000 µm correction, but public evidence is still a vendor proceedings presentation. https://siliconandsystems.com/en/articles/industry-memory-storage-2025/ https://siliconandsystems.com/en/articles/industry-memory-storage-2025/ Sat, 29 Aug 2026 15:00:00 GMT Thirty-four company-affiliated papers connect LPDDR, NAND, MRAM, GPU filesystems, KV-cache storage, archival glass, tape, zoned media, and cloud block stores. https://siliconandsystems.com/en/articles/meta-100k-gpu-network/ https://siliconandsystems.com/en/articles/meta-100k-gpu-network/ Sun, 30 Aug 2026 11:27:42 GMT Meta's SIGCOMM 2026 paper explains why a 100K-GPU fabric needs topology-aware initialization, on-demand communication state and dynamic queue-pair load balancing. https://siliconandsystems.com/en/articles/industry-architecture-micro-2025/ https://siliconandsystems.com/en/articles/industry-architecture-micro-2025/ Mon, 31 Aug 2026 13:51:07 GMT 35 verified company-affiliated MICRO papers connect architecture mechanisms to production software, model execution, memory behavior, reliability, and fleet operation. https://siliconandsystems.com/en/articles/aegaeon/ https://siliconandsystems.com/en/articles/aegaeon/ Tue, 25 Aug 2026 15:00:00 GMT In Alibaba's model marketplace, 94.1% of models drew 1.35% of requests yet occupied 17.7% of the GPUs. A SOSP 2025 paper moves serving decisions from the request to the token: preemptive model switching in under a second, seven models per GPU, and a production fleet cut from 1,192 H20s to 213. https://siliconandsystems.com/en/articles/byterobust/ https://siliconandsystems.com/en/articles/byterobust/ Tue, 25 Aug 2026 15:00:00 GMT Across 778,135 training jobs in three months, ByteDance logged 44,184 failures and 9,582 deliberate restarts. The SOSP 2025 paper on ByteRobust argues that at this scale reliability comes not from diagnosing root causes but from evicting suspects fast, treating engineers' own code changes as a failure class, and keeping a three-month 9,600-GPU job at 97% useful time. https://siliconandsystems.com/en/articles/cheriot-rtos-compartments/ https://siliconandsystems.com/en/articles/cheriot-rtos-compartments/ Mon, 31 Aug 2026 16:50:27 GMT CHERIoT RTOS co-designs capability hardware and an operating system for fine-grained, auditable, fault-tolerant compartments on low-cost devices. https://siliconandsystems.com/en/articles/copter-resource-allocation/ https://siliconandsystems.com/en/articles/copter-resource-allocation/ Mon, 31 Aug 2026 16:50:27 GMT COpter exploits small round-to-round changes in GPU, shard, and WAN allocation to solve large LP and MILP control problems continually. https://siliconandsystems.com/en/articles/diffkv-kv-compaction/ https://siliconandsystems.com/en/articles/diffkv-kv-compaction/ Mon, 31 Aug 2026 16:50:27 GMT Huawei's DiffKV differentiates precision and pruning, then compacts irregular free space in parallel on the GPU. https://siliconandsystems.com/en/articles/mercury-remote-gpu-memory/ https://siliconandsystems.com/en/articles/mercury-remote-gpu-memory/ Sat, 05 Sep 2026 15:00:00 GMT Mercury treats memory on another GPU as an explicit level of the hierarchy and searches computation, placement, and communication together. Across H100, A100, and L4 systems, the SOSP 2025 compiler finds schedules that match or exceed hand-built multi-GPU operators. https://siliconandsystems.com/en/articles/mercury-remote-memory-operators/ https://siliconandsystems.com/en/articles/mercury-remote-memory-operators/ Sun, 06 Sep 2026 01:39:31 GMT Mercury represents remote GPU memory, communication and loop order in one compiler IR. The SOSP 2025 work shows why topology-aware asynchronous schedules beat fixed collectives, especially when long-context operators cross node boundaries. https://siliconandsystems.com/en/articles/oasis-pcie-pooling/ https://siliconandsystems.com/en/articles/oasis-pcie-pooling/ Mon, 31 Aug 2026 00:04:17 GMT Oasis uses an existing CXL memory pool as a load/store and DMA path between hosts and remote PCIe devices. A software network engine doubles NIC utilization and fails over in 38 ms without a dedicated PCIe pooling switch. https://siliconandsystems.com/en/articles/prefillonly-llm-prefill/ https://siliconandsystems.com/en/articles/prefillonly-llm-prefill/ Mon, 31 Aug 2026 16:50:27 GMT PrefillOnly discards multi-token decoding assumptions, stores only last-layer KV state, and schedules known-size discriminative LLM requests by completion time. https://siliconandsystems.com/en/articles/rdma-device-live-migration/ https://siliconandsystems.com/en/articles/rdma-device-live-migration/ Mon, 31 Aug 2026 16:50:27 GMT NVIDIA exports ConnectX device state through a generic hypervisor interface and quiesces PCIe communication for transparent VM migration. https://siliconandsystems.com/en/articles/taichi-smartnic-scheduling/ https://siliconandsystems.com/en/articles/taichi-smartnic-scheduling/ Mon, 31 Aug 2026 16:50:27 GMT Alibaba's Tai Chi uses hybrid virtualization and a hardware workload probe to co-schedule SmartNIC control and data planes at microsecond precision. https://siliconandsystems.com/en/articles/ecoc-space-wavelength-switch/ https://siliconandsystems.com/en/articles/ecoc-space-wavelength-switch/ Sun, 30 Aug 2026 12:01:03 GMT Cambridge, NVIDIA, and Ghent-imec route commercial InfiniBand across a 4x4x8-wavelength silicon switch. The fabric works, but roughly 20 dB of path loss defines the next problem. https://siliconandsystems.com/en/articles/mitsubishi-400g-eml/ https://siliconandsystems.com/en/articles/mitsubishi-400g-eml/ Sun, 30 Aug 2026 12:01:03 GMT Mitsubishi Electric narrows an EML mesa and redesigns its submount for 400 Gb/s-per-lane optics. The components cross 100 GHz, while the bondless package reaches 85 GHz and 113.4 GBaud PAM4. https://siliconandsystems.com/en/articles/ai-cluster-network-ops/ https://siliconandsystems.com/en/articles/ai-cluster-network-ops/ Wed, 26 Aug 2026 15:00:00 GMT Industry papers from Alibaba and ByteDance show three different control points for AI-cluster networking: infer failures from training traffic, probe paths without host agents, and steer around global congestion. Their metrics are complementary, not interchangeable. https://siliconandsystems.com/en/articles/astral/ https://siliconandsystems.com/en/articles/astral/ Tue, 25 Aug 2026 15:00:00 GMT GPU FLOPS grew 4× from V100 to H100 while training demands grew 1500×, and the GPUs sold into China are weaker still. Tencent's answer at SIGCOMM 2025 is Astral: a three-tier fabric with no oversubscription anywhere, sized for 512K GPUs, plus the power plant, cooling, full-stack monitoring and a seconds-fast performance oracle that a rental business at that scale turns out to require. https://siliconandsystems.com/en/articles/bytetracker-agentless-probing/ https://siliconandsystems.com/en/articles/bytetracker-agentless-probing/ Sat, 29 Aug 2026 15:00:00 GMT ByteTracker replaces a server-wide probe-agent fleet with centralized probers, kernel-generated replies, and switch mirroring. In more than six months across ByteDance data centers, observed faults were localized within five seconds. https://siliconandsystems.com/en/articles/industry-circuits-2025/ https://siliconandsystems.com/en/articles/industry-circuits-2025/ Sat, 29 Aug 2026 15:00:00 GMT Six public industry papers from 2025 show precision moving into asynchronous pipelines, memory programming, package-scale imaging, and gradient-free learning. https://siliconandsystems.com/en/articles/infinitehbd/ https://siliconandsystems.com/en/articles/infinitehbd/ Tue, 25 Aug 2026 15:00:00 GMT NVL72-class domains buy their bandwidth with switch trays, and one switch failure degrades every attached node. At SIGCOMM 2025, StepFun and Lightelligence embed an optical circuit switch inside each 800G transceiver instead: rings of any size, node-level fault isolation, and an interconnect bill 31% of NVL-72's, at the price of giving up all-to-all. https://siliconandsystems.com/en/articles/sglb-global-load-balancing/ https://siliconandsystems.com/en/articles/sglb-global-load-balancing/ Sat, 29 Aug 2026 15:00:00 GMT SGLB distributes compact global congestion state to commodity Ethernet switches. Its prototype recovers from tested link failures in as little as 45 microseconds and raises All-to-All throughput by up to 60% under evaluated congestion. https://siliconandsystems.com/en/articles/skeletonhunter/ https://siliconandsystems.com/en/articles/skeletonhunter/ Sat, 29 Aug 2026 15:00:00 GMT SkeletonHunter infers the sparse network skeleton of containerized model training, then probes and localizes failures across overlay and physical layers. Six months of Alibaba Cloud production use found 4,816 failures with 98.2% precision and 99.3% recall. https://siliconandsystems.com/en/articles/alibaba-stellar-rdma/ https://siliconandsystems.com/en/articles/alibaba-stellar-rdma/ Mon, 31 Aug 2026 00:04:17 GMT Stellar replaces SR-IOV's fixed virtual functions with on-demand memory pinning, carries GPU memory type in the RNIC translation table, and sprays each connection across 128 paths. Alibaba reports a year of 400G production operation. https://siliconandsystems.com/en/articles/packaging-polymers-metrology/ https://siliconandsystems.com/en/articles/packaging-polymers-metrology/ Sun, 30 Aug 2026 23:57:42 GMT A NIST-led IEEE perspective shows why underfill, molding compound, adhesives, and dielectrics cannot be reduced to one datasheet Tg. Measurement method, cure history, moisture, and time change the package model. https://siliconandsystems.com/en/articles/ayar-ucie-optical-retimer/ https://siliconandsystems.com/en/articles/ayar-ucie-optical-retimer/ Sun, 30 Aug 2026 11:27:42 GMT Ayar Labs retimes a standard UCIe electrical interface into 16-wavelength optical links. Hot Chips 2025 results report 8.192 Tb/s bidirectional bandwidth and under 25 ns end-to-end latency. https://siliconandsystems.com/en/articles/celestial-photonic-fabric/ https://siliconandsystems.com/en/articles/celestial-photonic-fabric/ Sun, 30 Aug 2026 11:27:42 GMT Celestial AI embeds photonic I/O under compute and memory instead of consuming the package edge. Its Hot Chips 2025 deck reports 1.8 Tb/s in 1.9 mm² and a 7.2 Tb/s memory module. https://siliconandsystems.com/en/articles/lightmatter-passage-m1000/ https://siliconandsystems.com/en/articles/lightmatter-passage-m1000/ Sun, 30 Aug 2026 11:27:42 GMT Lightmatter's Passage M1000 stitches eight photonic tiles into a 4,000 mm² interposer complex with 1,024 SerDes and up to 114 Tb/s of aggregate transmit-plus-receive bandwidth. https://siliconandsystems.com/en/articles/industry-architecture-asplos-2025/ https://siliconandsystems.com/en/articles/industry-architecture-asplos-2025/ Mon, 31 Aug 2026 13:51:01 GMT 59 verified company-affiliated ASPLOS papers connect architecture mechanisms to production software, model execution, memory behavior, reliability, and fleet operation. https://siliconandsystems.com/en/articles/swiftrdma-rnic-scheduling/ https://siliconandsystems.com/en/articles/swiftrdma-rnic-scheduling/ Mon, 31 Aug 2026 00:04:17 GMT SwiftRDMA treats hidden RNIC resources as schedulable infrastructure. Its early prototype maps UARs, context caches, processing pipelines, and queue pairs to signals and actions that software can control. https://siliconandsystems.com/en/articles/mlperf-storage-v2/ https://siliconandsystems.com/en/articles/mlperf-storage-v2/ Wed, 26 Aug 2026 15:00:00 GMT MLPerf Storage 2.0 turns AI I/O into two auditable tests: keeping emulated accelerators fed during training and moving trillion-parameter checkpoints. Its most useful result is a method for finding where storage stops scaling. https://siliconandsystems.com/en/articles/anchornet-collaborative-streaming/ https://siliconandsystems.com/en/articles/anchornet-collaborative-streaming/ Mon, 31 Aug 2026 16:50:27 GMT ByteDance's AnchorNet keeps a TikTok channel on one broadcaster-to-CDN path while it switches between solo and collaborative streaming, then splices audio at sample granularity. https://siliconandsystems.com/en/articles/blitzscale-live-autoscaling/ https://siliconandsystems.com/en/articles/blitzscale-live-autoscaling/ Tue, 08 Sep 2026 15:22:20 GMT BlitzScale combines network-based weight distribution with temporary layer-level cooperation. A partially loaded instance relieves an overloaded peer before it can serve a complete model independently. https://siliconandsystems.com/en/articles/fast-acs-ordered-delivery/ https://siliconandsystems.com/en/articles/fast-acs-ordered-delivery/ Mon, 31 Aug 2026 16:50:27 GMT Google's Fast ACS separates durable ordered files from a 4 KB RMA cache so thousands of readers can tail one stream without turning a storage server into the fan-out bottleneck. https://siliconandsystems.com/en/articles/fide-crash-failure-detection/ https://siliconandsystems.com/en/articles/fide-crash-failure-detection/ Mon, 31 Aug 2026 16:50:27 GMT FiDe reserves an isolated OS and network path for heartbeats so a datacenter process crash can be reported in under 30 microseconds without false suspicions in the evaluated setting. https://siliconandsystems.com/en/articles/floating-point-accumulation-order/ https://siliconandsystems.com/en/articles/floating-point-accumulation-order/ Mon, 31 Aug 2026 16:50:27 GMT Microsoft Research's FPRev uses crafted numerical inputs to reveal undocumented CPU, GPU, BLAS, and Tensor Core accumulation orders without source code or traces. https://siliconandsystems.com/en/articles/greyhound-fail-slow/ https://siliconandsystems.com/en/articles/greyhound-fail-slow/ Sun, 30 Aug 2026 12:01:01 GMT GREYHOUND studies fail-slow incidents across Alibaba's 10,000-plus-GPU training fleet. Large jobs were affected more often and lost 34.59% of completion time on average, making diagnosis and staged mitigation an operational capacity problem. https://siliconandsystems.com/en/articles/kperfir-kernel-observability/ https://siliconandsystems.com/en/articles/kperfir-kernel-observability/ Tue, 08 Sep 2026 15:22:20 GMT KPerfIR carries loop and warp semantics into GPU profiling. Its FlashAttention case shows how a misplaced barrier can waste overlap, while instrumentation cost and trace reconstruction remain part of the measurement. https://siliconandsystems.com/en/articles/krr-kernel-replay/ https://siliconandsystems.com/en/articles/krr-kernel-replay/ Mon, 31 Aug 2026 16:50:27 GMT SmartX's KRR narrows deterministic record-replay to guest-kernel execution and splits input capture between guest instrumentation and the hypervisor, reducing cost for concurrent and kernel-bypass workloads. https://siliconandsystems.com/en/articles/marc-mobile-cloud-rendering/ https://siliconandsystems.com/en/articles/marc-mobile-cloud-rendering/ Mon, 31 Aug 2026 16:50:27 GMT Alibaba's MARC changes video bitrate frame by frame because shoppers value responsiveness during object motion and image quality while inspecting a still view. https://siliconandsystems.com/en/articles/mtuner-pcie-finetuning/ https://siliconandsystems.com/en/articles/mtuner-pcie-finetuning/ Mon, 31 Aug 2026 00:04:17 GMT mTuner treats frozen weights and runtime tensors as a changing memory budget. By gathering, discarding, checkpointing, and accumulating tensors at different times, it reduces communication where PCIe hurts most. https://siliconandsystems.com/en/articles/nic-receive-ring-dual-role/ https://siliconandsystems.com/en/articles/nic-receive-ring-dual-role/ Mon, 31 Aug 2026 16:50:27 GMT RxBisect separates empty-buffer allocation from packet delivery, allowing NIC receive capacity to absorb bursts without multiplying the packet-buffer working set across CPU cores. https://siliconandsystems.com/en/articles/okapi-decoupled-storage/ https://siliconandsystems.com/en/articles/okapi-decoupled-storage/ Tue, 08 Sep 2026 15:22:20 GMT Okapi independently chooses how widely a file is striped and which blocks share erasure-code protection. Its HDD experiments show better read efficiency and cheaper redundancy changes, with explicit degraded-read tradeoffs. https://siliconandsystems.com/en/articles/pageflex-ebpf-paging/ https://siliconandsystems.com/en/articles/pageflex-ebpf-paging/ Mon, 31 Aug 2026 16:50:27 GMT Google's PageFlex uses eBPF to move reclamation and prefetch decisions into user space while leaving Linux swap and the latency-critical page-fault path in the kernel. https://siliconandsystems.com/en/articles/primus-recommendation-training/ https://siliconandsystems.com/en/articles/primus-recommendation-training/ Mon, 31 Aug 2026 16:50:27 GMT ByteDance's Primus unifies YARN and Kubernetes resources, batch and stream data, and offline-online recommendation training behind one declarative job contract. https://siliconandsystems.com/en/articles/qimeng-xpiler/ https://siliconandsystems.com/en/articles/qimeng-xpiler/ Mon, 31 Aug 2026 16:50:27 GMT QiMeng-Xpiler decomposes tensor-code migration into LLM-assisted passes, repairs small incorrect regions with symbolic synthesis, and searches pass order and tuning parameters across four accelerator programming models. https://siliconandsystems.com/en/articles/serverless-cold-start-fork/ https://siliconandsystems.com/en/articles/serverless-cold-start-fork/ Mon, 31 Aug 2026 16:50:27 GMT Ant Group's AFaaS treats cold start as an end-to-end path, replacing general OCI interactions, pooling contended kernel resources, and forking from a hierarchy of language and function seeds. https://siliconandsystems.com/en/articles/sirius-gpu-memory-handover/ https://siliconandsystems.com/en/articles/sirius-gpu-memory-handover/ Sun, 06 Sep 2026 01:39:33 GMT SIRIUS colocates latency-sensitive inference with elastic training and hands GPU memory back at safe points inside a batch. The ATC 2025 paper reports sub-5 ms adjustment and 2.2× average training-throughput improvement. https://siliconandsystems.com/en/articles/skybridge-bounded-staleness/ https://siliconandsystems.com/en/articles/skybridge-bounded-staleness/ Mon, 31 Aug 2026 16:50:27 GMT Meta's Skybridge replicates recent write metadata through an independent, gap-detecting path so TAO can prove cache freshness without sending ordinary reads back to the primary database. https://siliconandsystems.com/en/articles/torpor-serverless-gpu/ https://siliconandsystems.com/en/articles/torpor-serverless-gpu/ Sun, 30 Aug 2026 12:01:01 GMT Torpor keeps inactive inference models in host memory and binds each arriving request to a four-GPU pool. Its Alibaba Cloud pilot reports 70% lower user cost, but the result depends on a precise memory, SLO, and workload contract. https://siliconandsystems.com/en/articles/waferllm-mesh-inference/ https://siliconandsystems.com/en/articles/waferllm-mesh-inference/ Sun, 06 Sep 2026 01:39:30 GMT WaferLLM maps prefill, decode and KV-cache movement onto a wafer-scale mesh instead of pretending that 850,000 local memories form one GPU. Its OSDI 2025 results expose both the promise and the portability limits of wafer-scale inference. https://siliconandsystems.com/en/articles/wlb-llm-4d-parallelism/ https://siliconandsystems.com/en/articles/wlb-llm-4d-parallelism/ Mon, 31 Aug 2026 16:50:27 GMT WLB-LLM balances long-context training by packing documents according to predicted work and selecting context-parallel sharding per micro-batch, rather than treating equal token counts as equal GPU loads. https://siliconandsystems.com/en/articles/xsched-xpu/ https://siliconandsystems.com/en/articles/xsched-xpu/ Wed, 26 Aug 2026 15:00:00 GMT XSched gives GPUs, NPUs, fixed-function ASICs and FPGAs one preemptible queue abstraction. Across ten devices, it cuts priority interference while preserving throughput, but the hardware's preemption level still sets the latency floor. https://siliconandsystems.com/en/articles/ai-physical-design-first/ https://siliconandsystems.com/en/articles/ai-physical-design-first/ Mon, 31 Aug 2026 05:40:52 GMT INSTA, LEGO-Size, and GOALPlace explain why physical design became the first chip-design domain where learned models can close a measurable industrial loop. https://siliconandsystems.com/en/articles/dcperf-cpu-benchmark/ https://siliconandsystems.com/en/articles/dcperf-cpu-benchmark/ Sat, 29 Aug 2026 15:00:00 GMT DCPerf models web, cache, analytics, ranking, and video services closely enough to project Meta production performance within 3.3% across four server generations. That changes benchmarking from leaderboard work to procurement infrastructure. https://siliconandsystems.com/en/articles/deepseek-scaleup/ https://siliconandsystems.com/en/articles/deepseek-scaleup/ Tue, 25 Aug 2026 15:00:00 GMT DeepSeek trained V3 on 2,048 H800 GPUs whose NVLink runs at 400 GB/s instead of 900. An ISCA 2025 industry paper turns that handicap into arithmetic: on 400G interconnects, MoE decode tops out near 67 tokens per second, against roughly 1,200 for a rack-scale fabric, and the authors spell out the hardware they want next. https://siliconandsystems.com/en/articles/llama3-parallelism/ https://siliconandsystems.com/en/articles/llama3-parallelism/ Sat, 29 Aug 2026 15:00:00 GMT Meta trained Llama 3 405B on 16,384 H100 GPUs with FSDP, tensor, pipeline, and context parallelism. The paper shows why efficiency at that scale depends on flexible schedules and debugging, not one ideal partition. https://siliconandsystems.com/en/articles/mtia/ https://siliconandsystems.com/en/articles/mtia/ Tue, 25 Aug 2026 15:00:00 GMT Meta's second-generation inference chip swaps HBM for 256 MB of SRAM over LPDDR, packs 24 chips into a server that matches eight GPUs, and cuts total cost of ownership by 44%. The ISCA 2025 paper spends its best pages on what silicon papers usually omit: memory errors at fleet scale, overclocking studies, a 40% power-budget cut, and firmware shipped 23 times in a year. https://siliconandsystems.com/en/articles/industry-architecture-isca-2025/ https://siliconandsystems.com/en/articles/industry-architecture-isca-2025/ Mon, 31 Aug 2026 13:51:05 GMT 43 verified company-affiliated ISCA papers connect architecture mechanisms to production software, model execution, memory behavior, reliability, and fleet operation. https://siliconandsystems.com/en/articles/intel-emib-fiber-cpo/ https://siliconandsystems.com/en/articles/intel-emib-fiber-cpo/ Sun, 30 Aug 2026 23:53:20 GMT Intel connects a 24-channel optical I/O chiplet to an XPU through EMIB and tests the fiber assembly through reflow and JEDEC stress. The paper treats optical loss as a manufacturing variable, not a laboratory constant. https://siliconandsystems.com/en/articles/ibm-graphite-substrate-cooling/ https://siliconandsystems.com/en/articles/ibm-graphite-substrate-cooling/ Sun, 30 Aug 2026 23:57:40 GMT IBM embeds an electrically isolated graphite sheet in an organic flip-chip substrate. A reported simulation lowers one concentrated hot spot by 4.8°C, but anisotropy and integration reliability decide whether the idea scales. https://siliconandsystems.com/en/articles/cxl-pcie-pooling/ https://siliconandsystems.com/en/articles/cxl-pcie-pooling/ Sun, 30 Aug 2026 23:48:25 GMT A HotOS paper from Microsoft and university researchers argues that a shared CXL memory pool can route I/O to remote NICs, SSDs and accelerators without a PCIe switch. The 100 Gbps prototype is promising, but the production control plane remains the real research problem. https://siliconandsystems.com/en/articles/leanattention-decode-tiles/ https://siliconandsystems.com/en/articles/leanattention-decode-tiles/ Sun, 06 Sep 2026 01:39:32 GMT LeanAttention turns exact softmax rescaling into a reduction and distributes long-context decode as balanced stream-K tiles. The MLSys 2025 paper reports 1.73× average attention speedup without approximating the result. https://siliconandsystems.com/en/articles/cxl-database-placement/ https://siliconandsystems.com/en/articles/cxl-database-placement/ Sun, 30 Aug 2026 23:48:25 GMT A PVLDB study with SAP participation measures four real CXL memory devices, vector scans, B+trees and TPC-H. Its useful result is not one latency ratio: keeping frequently accessed columns and temporary state local can place over 80% of table data on CXL while retaining at least 85% of local-only throughput. https://siliconandsystems.com/en/articles/bytecheckpoint-parallelism-agnostic/ https://siliconandsystems.com/en/articles/bytecheckpoint-parallelism-agnostic/ Sun, 06 Sep 2026 15:20:47 GMT ByteCheckpoint separates tensor identity from the parallel layout that wrote it, then reshares state while loading into a different framework, GPU count, or training stage. https://siliconandsystems.com/en/articles/odrp-remote-paging/ https://siliconandsystems.com/en/articles/odrp-remote-paging/ Mon, 31 Aug 2026 00:04:17 GMT ODRP turns native RDMA work requests into a 4 KB remote allocator. The result is a memory pool that keeps one-sided access and zero memory-node CPU use without reserving gigabyte slabs for every client. https://siliconandsystems.com/en/articles/energy-ai-grid/ https://siliconandsystems.com/en/articles/energy-ai-grid/ Wed, 26 Aug 2026 15:00:00 GMT The IEA projects datacenter electricity use to reach about 945 TWh in 2030, just under 3% of global demand. The harder engineering problem is that new gigawatts arrive in a few places, faster than grids can connect them. https://siliconandsystems.com/en/articles/flowcheck-network-checkpoint/ https://siliconandsystems.com/en/articles/flowcheck-network-checkpoint/ Sun, 06 Sep 2026 15:20:50 GMT FlowCheck mirrors ordinary all-reduce traffic to CPU checkpoint nodes, identifies complete gradient updates, and reconstructs training state without pausing GPU workers for a separate dump. https://siliconandsystems.com/en/articles/hybridflow/ https://siliconandsystems.com/en/articles/hybridflow/ Tue, 25 Aug 2026 15:00:00 GMT RLHF juggles four distributed LLMs whose outputs feed each other, and existing frameworks made that dataflow either flexible or fast, never both. ByteDance's EuroSys 2025 paper splits the difference by construction: one controller orchestrates the graph, many controllers run each model, and a resharding engine moves the actor between training and generation with zero duplicate weights. The result ships as verl. https://siliconandsystems.com/en/articles/pod-attention-hybrid-batching/ https://siliconandsystems.com/en/articles/pod-attention-hybrid-batching/ Sun, 06 Sep 2026 15:20:51 GMT POD-Attention fuses compute-heavy prefill and bandwidth-heavy decode attention at CTA granularity, using SM-aware scheduling to occupy resources that separate kernels leave idle. https://siliconandsystems.com/en/articles/vela-virtualized-llm-training/ https://siliconandsystems.com/en/articles/vela-virtualized-llm-training/ Sun, 06 Sep 2026 15:20:48 GMT Vela combines KVM virtual machines, SR-IOV NICs, GPU Direct, and RoCE on commercial hardware, showing how a cloud control plane can retain a direct GPU data path at cluster scale. https://siliconandsystems.com/en/articles/c4-training-efficiency/ https://siliconandsystems.com/en/articles/c4-training-efficiency/ Sat, 29 Aug 2026 15:00:00 GMT C4 uses the regular timing of training collectives to detect faulty nodes and plan long-lived network flows. Alibaba reports recovering 30% failure overhead and about 15% communication cost in production. https://siliconandsystems.com/en/articles/industry-architecture-hpca-2025/ https://siliconandsystems.com/en/articles/industry-architecture-hpca-2025/ Mon, 31 Aug 2026 13:51:03 GMT 40 verified company-affiliated HPCA papers connect architecture mechanisms to production software, model execution, memory behavior, reliability, and fleet operation. https://siliconandsystems.com/en/articles/meta-ml-reliability/ https://siliconandsystems.com/en/articles/meta-ml-reliability/ Sat, 29 Aug 2026 15:00:00 GMT Meta analyzed four million jobs and more than 150 million A100 GPU-hours across two research clusters. Reliability policy must cover rare giant jobs and the many smaller jobs that dominate queue and failure interactions. https://siliconandsystems.com/en/articles/mlperf-power/ https://siliconandsystems.com/en/articles/mlperf-power/ Sat, 29 Aug 2026 15:00:00 GMT MLPerf Power standardizes energy measurement from microwatt edge devices to megawatt datacenters. Its 1,841 measurements show why accuracy, data movement, and system boundary must stay attached to every efficiency claim. https://siliconandsystems.com/en/articles/ananke-filesystem-recovery/ https://siliconandsystems.com/en/articles/ananke-filesystem-recovery/ Mon, 31 Aug 2026 16:50:27 GMT Ananke gives a user-space filesystem a separate process-crash recovery path, reconstructing volatile application-visible state from a protected operation log instead of forcing every update to storage. https://siliconandsystems.com/en/articles/atomicdisk-tee-storage/ https://siliconandsystems.com/en/articles/atomicdisk-tee-storage/ Mon, 31 Aug 2026 16:50:27 GMT AtomicDisk adds sync atomicity to SGX protected storage so cache-evicted transient disk states cannot be captured and replayed as if the application had committed them. https://siliconandsystems.com/en/articles/flacio-container-images/ https://siliconandsystems.com/en/articles/flacio-container-images/ Mon, 31 Aug 2026 16:50:27 GMT FlacIO traces service startup once, compacts the required pages into a contiguous runtime image, and injects them into a kernel page cache to remove network request amplification from lazy container loading. https://siliconandsystems.com/en/articles/mooncake/ https://siliconandsystems.com/en/articles/mooncake/ Tue, 25 Aug 2026 15:00:00 GMT Moonshot AI serves its long-context chatbot from a cluster-wide pool of CPU memory and SSDs that caches every reusable KV prefix. The FAST 2025 paper behind Kimi's serving platform shows the arithmetic of trading storage for computation: up to 498% more requests within SLOs, and a fleet that handles 115% more traffic than its predecessor. https://siliconandsystems.com/en/articles/ibm-telum-ii/ https://siliconandsystems.com/en/articles/ibm-telum-ii/ Sun, 30 Aug 2026 11:27:42 GMT IBM Telum II combines eight 5.5 GHz cores, 360 MB of on-chip cache, AI acceleration and an I/O DPU on a 43-billion-transistor Samsung 5 nm die. https://siliconandsystems.com/en/articles/hbm-local-clock-regeneration/ https://siliconandsystems.com/en/articles/hbm-local-clock-regeneration/ Mon, 31 Aug 2026 10:19:31 GMT An ISSCC 2025 circuit sends one phase-rotating reference across an HBM die and reconstructs four 2-to-5 GHz clocks beside each DQ group. The 850 µW generator filters jitter and starts on the first useful edge, but the evidence remains a clock-network result rather than a full HBM power measurement. https://siliconandsystems.com/en/articles/lumorph-photonic-rack/ https://siliconandsystems.com/en/articles/lumorph-photonic-rack/ Sun, 30 Aug 2026 12:01:03 GMT Cornell and Lightmatter move optical circuit switching underneath the accelerator. Their LIGHTPATH device reconfigures in 3.7 microseconds; the rack-scale gains remain simulated. https://siliconandsystems.com/en/articles/laser-forwarded-cpo-codesign/ https://siliconandsystems.com/en/articles/laser-forwarded-cpo-codesign/ Sun, 30 Aug 2026 23:53:30 GMT A Journal of Lightwave Technology model puts laser loss, modulator drive and host equalization inside one 224 Gb/s coherent CPO boundary. Moving one equalizer tap changes the projected total from 2.0 to 1.2 pJ/b. https://siliconandsystems.com/en/articles/alphachip-production-silicon/ https://siliconandsystems.com/en/articles/alphachip-production-silicon/ Mon, 31 Aug 2026 05:44:41 GMT AlphaChip did not generate a whole processor. It learned to place large circuit blocks inside a conventional implementation flow, and Google reports that the method reached three TPU generations and Axion CPUs that now run production services. https://siliconandsystems.com/en/articles/industry-circuits-2024/ https://siliconandsystems.com/en/articles/industry-circuits-2024/ Sat, 29 Aug 2026 15:00:00 GMT Nine publicly accessible industry papers from the leading solid-state-circuit venues show where measured silicon changed the design argument in 2024. https://siliconandsystems.com/en/articles/industry-memory-storage-2024/ https://siliconandsystems.com/en/articles/industry-memory-storage-2024/ Sat, 29 Aug 2026 15:00:00 GMT Thirty-five company-affiliated papers show how HBM, LPDDR, NAND, CXL memory, flash caches, file systems, and cloud storage became one placement problem in 2024. https://siliconandsystems.com/en/articles/mi300a-package/ https://siliconandsystems.com/en/articles/mi300a-package/ Sat, 29 Aug 2026 15:00:00 GMT AMD's MI300A joins 24 Zen 4 cores, six CDNA 3 GPU chiplets, and 128 GB of HBM3 in one coherent package. The important result is not density alone, but the removal of the CPU-to-GPU copy boundary. https://siliconandsystems.com/en/articles/tensor-contraction-processor/ https://siliconandsystems.com/en/articles/tensor-contraction-processor/ Sat, 29 Aug 2026 15:00:00 GMT FuriosaAI's 5 nm Tensor Contraction Processor treats a tensor contraction, not a fixed matrix tile, as the primitive. Coarse processing elements split into slices so one 150 W chip can follow changing inference shapes. https://siliconandsystems.com/en/articles/routable-pcie-bench/ https://siliconandsystems.com/en/articles/routable-pcie-bench/ Mon, 31 Aug 2026 00:04:17 GMT rPCIeBench measures what changes when PCIe crosses non-transparent bridges. One-way latency rises from 379.0 to 868.6 ns, while credit flow and directional links create predictable bandwidth-sharing rules. https://siliconandsystems.com/en/articles/traffic-reprofiling-deadlines/ https://siliconandsystems.com/en/articles/traffic-reprofiling-deadlines/ Sun, 30 Aug 2026 01:49:33 GMT Traffic reprofiling spends part of a hard latency budget at ingress to smooth bursts before they traverse multiple links. A Google-affiliated journal study shows when that trade can lower required bandwidth and where its assumptions limit deployment. https://siliconandsystems.com/en/articles/honeycomb-pcie-smartnic/ https://siliconandsystems.com/en/articles/honeycomb-pcie-smartnic/ Mon, 31 Aug 2026 00:04:17 GMT Honeycomb keeps a large B-tree in host DRAM while an FPGA SmartNIC executes GET and SCAN. Caching, segmented nodes, out-of-order requests, and wait-free reads turn PCIe from a fatal bottleneck into a managed hierarchy. https://siliconandsystems.com/en/articles/roce-hyperscale-limits/ https://siliconandsystems.com/en/articles/roce-hyperscale-limits/ Mon, 31 Aug 2026 00:04:17 GMT RoCE preserved Ethernet deployment while importing lossless RDMA semantics. At hyperscale, PFC headroom, congestion trees, go-back-N recovery, connection state, headers, security, and FEC become one coupled protocol cost.